Clock Level Simulations of an Atm Switch

We simulate an ATM VPI-switch with pipelined (or shared-slot data buuer) and output buuering. Our experiments for 2 2 and 4 4 switches under constant and time-variant traac indicate that both switches and memory organizations have near-optimal through-put. Assuming switches are of similar technology, multistage network experiments under constant traac indicate that 4 4 and 16 16 networks conngured with smaller 22 switches achieve higher performance. However, networks conngured with larger switches are more cost-eecient.